1. Field of the Invention
The invention relates to diagnosis and repair of defects of memories on chips. In particular, the invention relates to an on-chip diagnosis method and to an on-chip diagnosis block.
2. Description of the Related Art
Memories are much denser than logic circuits. Since many bits need to be packed as tightly as possible, defects are part of any fabrication process. In order to compensate for these defects and increase the yield, most memories have some type of redundancy: internal redundancy (e.g., input/output-IO or WordLine-WL redundancy) or external redundancy (e.g., utilizing external word-registers). Most fails on memories are single cell fails, non-single cell type defects (IO) or clusters of fails. If one wishes to maximize an increase in yield, then one has to mix the different types of available redundancies (internal and external).
Several solutions to fix defects inside memories with redundancy are utilized according to the state of the art. For example, external redundancy utilizes registers to replace failing words. This type of redundancy is well suited for single bit or small cluster fails. However, this type of redundancy is not well suited for bit-line (BL) or IO oriented failures. Internal redundancy (utilizing WordLine and/or IO line replacement) is well suited for clusters of fails and non-single cell types defects (e.g., IO or WordLine defects). The main disadvantage of internal redundancy is that this solution increases the access and cycle time in the memory block because one has to compare the actual address with information stored in fuses.
Hybrid approaches, for example, that utilize a combination of word, wordline, and bitline redundancy are also possible. Advantages to one such approach are described in the commonly-assigned (with the present application) European patent application EP 03002698.3, entitled “Memory Built-In Self Repair (MBISR) circuits/devices and method for repairing a memory comprising a Memory Built-In Self Repair (MBISR) structure”. The main disadvantages of such hybrid approaches are that more than one BIST (Built-In Self Test) runs are needed (e.g., at least three), the usage of redundant wordline implies a loss in performances, the repair solution is hard-coded (first IO/BL, the WordLine, and finally Words), in some cases memories that could be repaired will be discarded and the additional logic needed may be relatively expensive, in particular because a lot of comparisons are performed.
Accordingly, a need exists for an on chip diagnosis logical block and method for memory repair